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Aldec Inc. - The Design Verification Company
Aldec - The Design Verification Company
Simulation
Insight
Verification
EDA
Synthesis
Schematic
vhdl
VERILOG
Cadence
MTI
Xilinx
Orcad
Synopsys
Mentor Graphics
Avnet
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ALDEC
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Nu Horizons
Active-HDL
VHDL Simulation
Verilog Simulation
Active-CAD
Active-VHDL
Aldec Inc.
EDIF Simulation
Model Technologies
www.aldec-kharkov.com - 2009-02-09
Dr. Fallot-Burghardt - ASIC Design & Consulting
Dr. Fallot-Burghardt, Partner für Analog, Digital- und Mixed-Signal ASICs, Consulting, Freelancing
Consulting
digital
Beratung
Contractor
Contracting
Freelancer
analog
Chip
Timing
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ASIC
Synthesis
Schematic
VHDL
Verilog
Ambit
Cadence
Spectre
Pspice
mixed-signal
Synopsys
IC Craftsman
BuildGates
CellEnsemble
Place&Route
www.fallot-burghardt.com - 2009-02-07
ASICS.ws - Your Partner for IP Cores, ASIC/FPGA Design, Synthesis and Verification -
ASICS.ws - Solutions for your ASIC/FPGA and system design needs -
Free
Design
Layout
Design Services
Verification
RTL
ASICS
Synthesis
IEEE
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Schematic
PCB Design
VHDL
Verilog
LSI
Cadence
VLSI
OrCAD
IP Cores
Synopsys
FPU
Gate Array
754
854
Custom IC
Cheap Service
Schematic Entry
Design Compiler
Free IP
Free IP Cores
Deep Chip
www.asics.ws - 2009-03-09
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